Some conventional SRAMs feature a function, called in jargon flash-clear, by which all of the memory cells are set at a time in a prescribed state (conventionally, a “0” logic state). The flash-clear function, triggered upon assertion of a control signal external to the memory, allows initialising the memory, e.g. for resetting or testing purposes.
Conventionally, the memory flash clear is performed by simultaneously selecting all the word lines of the memory cell array, so as to select all the memory cells, and forcing all the bit lines of the memory cell array to the reference potential (ground). In this way, all the memory cells switches to the “0” logic state.
A drawback of this approach, especially for medium- or large-size memory cell arrays, is the relatively high peak value of the current sunk by the memory during the flash-clear operation. The supply voltage level and the reference voltage level seen by the memory can in fact be affected by the relatively high peak current to such an extent as to undermine the functionality of part or all of the integrated circuit. In the worst case, the integrated circuit may be damaged or even destroyed by electromigration phenomena.
One solution proposed to overcome this problem by reducing the flash-clear peak current is disclosed in U.S. Pat. No. 4,949,308. The memory cell array is divided into a plurality of memory cell groups which are driven at mutually different timings for flash-clearing by means of a plurality of delay circuits connected in cascade, to which the flash-clearing signal is applied.
The solution proposed in that document imposes changes to the row and column decoding circuits. As a consequence, it cannot be easily implemented in existing SRAM designs lacking the flash-clear function.